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19-2220; Rev 1; 11/04
KIT ATION EVALU E AILABL AV
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
General Description Features
+2.375V to +3.8V Supply for Differential HSTL/LVPECL Operation -2.375V to -3.8V Supply for Differential LVECL Operation Two Selectable Differential Inputs Synchronous Output Enable/Disable 20ps Output-to-Output Skew 360ps Propagation Delay Guaranteed 400mV Differential Output at 1.5GHz On-Chip Reference for Single-Ended Inputs Input Biased Low when Left Open Pin Compatible with MC100LVEP14
MAX9315
The MAX9315 low-skew, 1-to-5 differential driver is designed for clock and data distribution. This device allows selection between two inputs. The selected input is reproduced at five differential outputs. The differential inputs can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9315 features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, this device operates over a +2.375V to +3.8V supply range, allowing highperformance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, this device operates with a -2.375V to -3.8V supply. The MAX9315 is offered in a space-saving 20-pin TSSOP package.
Applications
Precision Clock Distribution Low-Jitter Data Repeater Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE
PART MAX9315EUP
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 20 TSSOP
Pin Configuration
Typical Application Circuit
TOP VIEW
QO 1 Q0 2
MAX9315
20 VCC Q D 19 EN 18 VCC 17 CLK1 16 CLK1 15 VBB 14 CLK0 13 CLK0 12 SEL 11 VEE TSSOP
MAX9315
ZO = 50 Q_
RECEIVER
Q1 3 Q1 4 Q2 5
ZO = 50 Q_
Q2 6 Q3 7 Q3 8
50 50
Q4 9 Q4 10
VTT = VCC - 2.0V
Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
ABSOLUTE MAXIMUM RATINGS
VCC - VEE...............................................................................4.1V Inputs (CLK_, CLK_, SEL, EN) to VEE ...........................................(VEE - 0.3V) to (VCC + 0.3V) CLK_ to CLK_ ....................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 20-Pin TSSOP (derate 7.69mW/C above +70C) .......615mW Multilayer PC Board 20-Pin TSSOP (derate 10.9mW/C above +70C) .......879mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin TSSOP .........................................................+130C/W Multilayer PC Board 20-Pin TSSOP ...........................................................+91C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC Board 20-Pin TSSOP ..........................................................+9.6C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ............................................................+20C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Inputs and Outputs) .......................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 3.8V, outputs loaded with 50 1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN VCC 1.225 VEE VIH(MAX), VIL(MIN) -500 TYP MAX MIN VCC 1.225 VEE -500 +25C TYP MAX MIN VCC 1.225 VEE -500 +85C TYP MAX UNITS
SINGLE-ENDED INPUTS (SEL, EN) Input High Voltage Input Low Voltage Input Current VIH VIL IIN VCC VCC 1.625 500 VCC VCC 1.625 500 VCC VCC 1.625 500 V V A
DIFFERENTIAL INPUTS (CLK_, CLK_) Single-Ended Input High Voltage (Note 4) Single-Ended Input Low Voltage (Note 4) High Voltage of Differential Input Low Voltage of Differential Input VIH VBB connected to CLK_, Figure 1 VCC 1.225 VCC VCC 1.225 VCC VCC 1.225 VCC V
VIL
VBB connected to CLK_, Figure 1
VEE VEE + 1.2 VEE
VCC 1.625 VCC VCC 0.1
VEE VEE + 1.2 VEE
VCC 1.625 VCC VCC 0.1
VEE VEE + 1.2 VEE
VCC 1.625 VCC VCC 0.1
V
VIHD VILD
V V
2
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1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 2.375V to 3.8V, outputs loaded with 50 1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS For (VCC - VEE) < +3.0V For (VCC - VEE) +3.0V VIH, VIL, VIHD, VILD -40C MIN 0.1 0.1 -150 TYP MAX VCC VEE 3.0 150 MIN 0.1 0.1 -150 +25C TYP MAX VCC VEE 3.0 150 MIN 0.1 0.1 -150 +85C TYP MAX VCC VEE 3.0 150 A UNITS
MAX9315
Differential Input Voltage Input Current OUTPUTS (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage REFERENCE Reference Voltage Output (Note 5) SUPPLY Supply Current (Note 6)
VIHD VILD IIN
V
VOH
Figure 1
VCC 1.145
VCC - VCC 0.865 1.145
VCC - VCC 0.865 1.145
VCC 0.865
V
VOL VOH VOL
Figure 1
VCC 1.945 550
VCC - VCC 1.695 1.945 910 550
VCC - VCC 1.695 1.945 910 550
VCC 1.695 910
V
Figure 1
mV
VBB
IBB = 0.5mA
VCC 1.525
VCC - VCC 1.325 1.525
VCC - VCC 1.325 1.525
VCC 1.325
V
IEE
41
48
45
55
49
65
mA
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3
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 7)
-40C PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS ps
Differential Inputto-Output Delay Output-to-Output Skew (Note 8) Part-to-Part Skew (Note 9) Added Random Jitter (Note 10) Added Deterministic Jitter (Note 10) Switching Frequency Output Rise/Fall Time (20% to 80%)
tPLHD, tPHLD tSKOO tSKPP tRJ
Figure 2
290
400
310
440
300
520
ps
5
30 110
20
40 130
20
50 220
ps ps ps (RMS)
fIN = 1.5GHz clock 1.5Gbps 2E23-1 PRBS pattern (VOH - VOL) 400mV, Figure 2 Figure 2
0.8
1.2
0.8
1.2
0.8
1.2
tDJ
50
70
50
70
50
70
ps (p-p)
fMAX
1.5
1.5
1.5
GHz
tR, tF
80
120
90
130
90
145
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25C and guaranteed by design over the full operating temperature range. Note 4: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V. Note 5: Use VBB only for inputs that are on the same device as the VBB reference. Note 6: All pins open except VCC and VEE. Note 7: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 10: Device jitter added to the input signal.
4
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1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
Typical Operating Characteristics
(VCC = +3.3V, VEE = 0, VIHD = VCC - 1V, VILD = VCC - 1.15V, input transition time = 125ps (20% to 80%), fIN = 2GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9315 toc01
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY
MAX9315 toc02
TRANSITION TIME vs. TEMPERATURE
MAX9315 toc03
50 49 48 SUPPLY CURRENT (mA) 47 46 45 44 43 42 41 40 -40 -15 10 35 60 ALL PINS ARE OPEN EXCEPT VCC AND VEE
900 DIFFERENTIAL OUTPUT VOLTAGE (mV) 800 700 600 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5
140 130 TRANSITION TIME (ps) 120 tR 110 100 tF 90 80
85
3.0
-40
-15
10
35
60
85
TEMPERATURE (C)
FREQUENCY (GHz)
TEMPERATURE (C)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9315 toc04
PROPAGATION DELAY vs. TEMPERATURE
MAX9315 toc05
370
390 380 PROPAGATION DELAY (ps) 370 360 350 340 330
PROPAGATION DELAY (ps)
364
358
352
346
340 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VIHD (V)
-40
-15
10
35
60
85
TEMPERATURE (C)
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5
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18, 20 NAME Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 VEE SEL CLK0 CLK0 VBB CLK1 CLK1 VCC FUNCTION Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q4 Output. Typically terminate with 50 resistor to VCC - 2V. Negative Supply Voltage Clock Select Input (Single Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. The SEL threshold is equal to VBB. Noninverting Differential Clock Input 0. Internal 75k pulldown to VEE. Inverting Differential Clock Input 0. Internal 75k pullup to VCC and 75k pulldown to VEE. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise, leave open. Noninverting Differential Clock Input 1. Internal 75k pulldown to VEE. Inverting Differential Clock Input 1. Internal 75k pullup to VCC and 75k pulldown to VEE. Positive Supply Voltage. Bypass VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock input when EN is low. Outputs are synchronously driven low on the falling edge of the selected clock input when EN is high.
19
EN
Detailed Description
The MAX9315 is a low-skew, 1-to-5 differential driver designed for clock or data distribution. A 2-to-1 MUX selects one of the two differential clock inputs, CLK0, CLK0 or CLK1, CLK1. The MUX is switched by the single-ended SEL input. A logic low selects the CLK0, CLK0 input and a logic high selects the CLK1, CLK1 input. The SEL logic threshold is set by the internal voltage reference VBB. SEL can be driven to VCC and VEE or by a single-ended LVPECL/LVECL signal. The selected input is reproduced at five differential outputs.
toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are set to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN is equal to VBB.
Supply
For interfacing to differential HSTL and LVPECL signals, the V CC range is from +2.375V to +3.8V (with VEE grounded), allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For interfacing to differential LVECL, the VEE range is -2.375V to -3.8V (with VCC grounded). Output levels are referenced to V CC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and
Synchronous Enable
The MAX9315 is synchronously enabled and disabled with outputs in the low state to eliminate shortened clock pulses. EN is connected to the input of an edgetriggered D flip-flop. After power-up, drive EN low and
6
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1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
VEE connected to ground, the outputs are LVPECL. The outputs are LVECL when VCC is connected to ground and VEE is connected to a negative supply. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, leave it open. The V BB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use VBB only for inputs that are on the same device as the VBB reference.
MAX9315
Input Bias Resistors
When the inputs are open, the internal bias resistors set the inputs to low state. The inverting inputs (CLK0 and CLK1) are each biased with a 75k pullup to VCC and a 75k pulldown to VEE. The noninverting inputs (CLK0 and CLK1) are each biased with a 75k pulldown to VEE.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC (if the VBB reference is not used, it can be left open).
Differential Clock Input Limits
The maximum magnitude of the differential signal applied to the clock input is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously.
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9315. Connect high-frequency input and output signals with 50 characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces.
Single-Ended Clock Input and VBB
The differential clock inputs can be configured to accept single-ended inputs. This is accomplished by connecting the on-chip reference voltage, VBB, to the inverting or noninverting input of a differential input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the singleended input signal to CLK0. Similarly, an inverting configuration is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0. With a differential input configured as single ended (using VBB), the single-ended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. Note that single-ended input must be at least VBB 100mV or a differential input of at least 100mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. If VBB is used, the supply must be in the VCC - VEE = +2.725V to +3.8V range because one of the inputs must be VEE + 1.2V or higher for proper input stage operation. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (singleended) input swings below it. Therefore, minimum VBB = V EE + 1.2V. The minimum V BB output of the MAX9315 is VCC - 1.525V. Substituting the minimum VBB output into VBB = VEE + 1.2V results in a minimum supply of +2.725V. Rounding up to standard supplies gives the single-ended operating supply range of VCC VEE = +3.0V to +3.8V.
Output Termination
Terminate outputs with 50 to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 616 PROCESS: Bipolar
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7
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
CLK CLK (CLK IS CONNECTED TO VBB) VIH VBB VIL
Q_ VOH - VOL Q_
VOH
VOL
Figure 1. MAX9315 Switching Characteristics with Single-Ended Input
CLK VIHD - VILD CLK
VIHD
VILD
tPLHD
tPHLD
Q_ VOH - VOL Q_
VOH
VOL
80% 0 (DIFFERENTIAL) 20% Q_ - Q_ tR
80% 0 (DIFFERENTIAL) 20%
tF
Figure 2. MAX9315 Timing Diagram
8
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1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
EN tS tH tS tH
CLK CLK Q_ Q_
tPLHD OUTPUTS ARE LOW OUTPUTS STAY LOW
Figure 3. MAX9315 EN Timing Diagram
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9
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9315
Functional Diagram
VCC
Q0
75k CLK0
Q0
Q1 CLK0 Q1 75k 75k Q2 0 VCC Q2
VEE
VEE
75k CLK1
1
Q3
Q3 CLK1 Q4 75k 75k Q4 VEE SEL Q EN VBB D VEE
VCC
MAX9315
10
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1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9315
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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